Product Summary

The M81C55-5 is a 2048-Bit CMOS static RAM with I/O ports and timer. The device has a 2k-bit static RAM (256 bytes) with parallel I/O ports and a timer. The M81C55-5 uses silicon gate CMOS technology and consumes a standby current of 100 micro ampere, maximum, while the chip is not selected. Featureing a maximum access time of 400 ns, the device can be used in an MSM80C85AH system without using wait states. The parallel I/O consists of two 8-bit ports and one 6-bit port (both general purpose). The M81C55-5 also contains a 14-bit programmable counter/timer which may be used for sequence-wave generation or terminal count-pulsing.

Parametrics

M81C55-5 absolute maximum ratings: (1)Power Supply Voltage, VCC: –0.5 to +7V; (2)Input Voltage, VIN: –0.5 to VCC +0.5V; (3)Output Voltage, VOUT: –0.5 to VCC +0.5V; (4)Storage Temperature, TSTG: –55 to +150℃; (5)Power Dissipation, PD: 0.7W.

Features

M81C55-5 features: (1)High speed and low power achieved with silicon gate CMOS technology; (2)256 words x 8bits RAM; (3)Single power supply, 3 to 6 V; (4)Completely static operation; (5)On-chip address latch; (6)8-bit programmable I/O ports (port A and B); (7)TTL Compatible; (8)RAM data hold characteristic at 2 V; (9)6-bit programmable I/O port (port C); (10)14-bit programmable binary counter/timer; (11)Multiplexed address/data bus; (12)Direct interface with MSM80C85AH; (13)40-pin Plastic DIP (DIP40-P-600-2.54): (Product name: MSM81C55-5RS); (14)44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM81C55-5JS); (15)44-pin Plastic QFP (QFP44-P-910-0.80-2K): (Product name: MSM81C55-5GS-2K).

Diagrams

M81C55-5 block diagram