Product Summary

The ADSP2181KS-133 is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP2181KS-133 combines the ADSP-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory. The ADSP2181KS-133 integrates 80K bytes of on-chip memory configured as 16K words (24-bit) of program RAM, and 16K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equipment. The ADSP2181KS-133 is available in 128-lead TQFP and 128-lead PQFP packages.

Parametrics

ADSP2181KS-133 absolute maximum ratings: (1)Input Voltage: –0.3V to VDD+0.3V; (2)Output Voltage Swing: –0.3V to VDD+0.3V; (3)Operating Temperature Range (Ambient): –40℃ to +85℃; (4)Storage Temperature Range: –65℃ to +150℃; (5)Lead Temperature (5 sec) TQFP: +280℃; (6)Lead Temperature (5 sec) PQFP: +280℃.

Features

ADSP2181KS-133 features: (1)25 ns Instruction Cycle Time from 20 MHz Crystal at 5.0 Volts; (2)40 MIPS Sustained Performance; (3)Single-Cycle Instruction Execution; (4)Single-Cycle Context Switch; (5)Low Power Dissipation in Idle Mode; (6)integration; (7)ADSP-2100 Family Code Compatible, with Instruction Set Extensions; (8)Six External Interrupts; (9)13 Programmable Flag Pins Provide Flexible System Signaling; (10)ICE-Port Emulator Interface Supports Debugging in Final Systems; (11)4 MByte Memory Interface for Storage of Data Tables and Program Overlays; (12)8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers; (13)I/O Memory Interface with 2048 Locations Supports Parallel Peripherals.

Diagrams

ADSP2181KS-133 block diagram

ADSP-2100
ADSP-2100

Other


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